Lab 5 Background Knowledge

Translation Levels

在 Lab 5 會用到共 4 層 translation levels:

  • page global directory (PGD)
  • page upper directory (PUD)
  • page middle directory (PMD)
  • page table entry(PTE)

Page vs Page frame vs Page table


Page : A chunk of virtual memory pointed by one entry of PTE.

Block : A chunk of virtual memory pointed by one entry of PUD or PMD.

Page frame : A chunk of physical memory.

Page table : A page frame whose entries point to the next level page tables, blocks, or pages. In this documentation, PGD, PUD, PMD and PTE are all called page table.

Page Descriptor

Memory Attribute

  • Unprivileged eXecute Never (UXN) and Privileged eXecute Never (PXN) are execution permissions.
  • AF is the access flag.
  • SH is the shareable attribute.
  • AP is the access permission.
  • NS is the security bit, but only at EL3 and Secure EL1.
  • Indx is the index into the MAIR_ELn

Virtual Address: 4KB Granule

AArch64 memory layout

In 64 bit virtual memory system, the upper address space is for kernel and the lower address space is for user.

圖片來自 Lab 5 spec

Configuration in Lab 5

  • Disable instruction cache.
  • Disable data cache.
  • Addresible region is 48 bit.
  • Page granule size is 4KB.
  • Not use address space ID (ASID).


ARMv8-A Address Translation

The AArch64 Virtual Memory System Architecture of ARMv8-A Architecture Reference

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