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Registers

System Registers

Doc: https://developer.arm.com/docs/ddi0595/h/aarch64-system-registers

Exception

Vector Table

  • VBAR_EL1 (Vector Base Address Register (EL1))
  • VBAR_EL2 (Vector Base Address Register (EL2))
  • VBAR_EL3 (Vector Base Address Register (EL3))

ESR

  • ESR_EL1 (Exception Syndrome Register (EL1))
  • ESR_EL2 (Exception Syndrome Register (EL2))
  • ESR_EL3 (Exception Syndrome Register (EL3))

ELR

  • ELR_EL1 (Exception Link Register (EL1))
  • ELR_EL2 (Exception Link Register (EL2))
  • ELR_EL3 (Exception Link Register (EL3))

PSTATE

  • SPSR_EL1 (Saved Program Status Register (EL1))
  • SPSR_EL2 (Saved Program Status Register (EL2))
  • SPSR_EL3 (Saved Program Status Register (EL3))

System Control

Architectural Feature Access Control

  • CPACR_EL1 (Architectural Feature Access Control Register)

Stack

Timer

  • CNTP_CTL_EL0 (Counter-timer Physical Timer Control register)
  • CNTPCT_EL0 (Counter-timer Physical Count register)
  • CNTP_CVAL_EL0 (Counter-timer Physical Timer CompareValue register)
    • 當 CNTPCT_EL0 >= CNTP_CVAL_EL0 時會觸發 Interrupt
  • CNTP_TVAL_EL0 (Counter-timer Physical Timer TimerValue register)
    • 當寫入 TVAL 時,其實是將 CVAL 設為 CNTPCT_EL0 加上寫入 TVAL 的值

Ref: QA7_rev3.4 page 9

Hypervisor level

  • HCR_EL2 (Hypervisor Configuration Register)

Multi-tasking

Virtual Memory

MAIR_EL1

MMU has different memory access policies for different memory regions.

  • Memory access policies are encoded as attributes and store in MAIR.
  • To select attribute for a certain memory region, each page table’s entry contains the index to the attribute.

When MMU get a virutal address, it get the index from the page table’s entry and looks up MAIR to get the memory attribute. Then, it access the memory with different access policies.

MMIO

#define MMIO_BASE 0x3F000000

Mailboxes

#define MBOX_Base (MMIO_BASE + 0xB880)
REGISTERADDRESS
ReadMBOX_Base
PollMBOX_Base + 0x10
SenderMBOX_Base + 0x14
StatusMBOX_Base + 0x18
ConfigurationMBOX_Base + 0x1C
WriteMBOX_Base + 0x20

Ref: http://magicsmoke.co.za/?p=284

PL011 UART

#define UART0_BASE      (MMIO_BASE + 0x201000)
REGISTERADDRESS
UART0_DRUART0_BASE
UART0_FRUART0_BASE + 0x18
UART0_IBRDUART0_BASE + 0x24
UART0_FBRDUART0_BASE + 0x28
UART0_LCRHUART0_BASE + 0x2C
UART0_CRUART0_BASE + 0x30
UART0_IMSCUART0_BASE + 0x38
UART0_RISUART0_BASE + 0x3C
UART0_MISUART0_BASE + 0x40
UART0_ICRUART0_BASE + 0x44

Typical baud rates and integer and fractional divisors
Typical baud rates and integer and fractional divisors

Doc: PrimeCell® UART (PL011)

UARTCR

The UARTCR register is the control register

Ref: PrimeCell® UART (PL011) - 3.3.8

UARTIBRD

The UARTIBRD register is the integer part of the baud rate divisor value. All the bits are cleared to 0 on reset.

Baud rate divisor BAUDDIV = (FUARTCLK/ {16 * Baud rate})

Ref: PrimeCell® UART (PL011) - 3.3.5

UARTFBRD

The UARTFBRD register is the fractional part of the baud rate divisor value. All the bits are cleared to 0 on reset.

Ref: PrimeCell® UART (PL011) - 3.3.6

UARTLCR_H

The UARTLCR_H register is the line control register. This register accesses bits 29 to 22 of the UART bit rate and line control register, UARTLCR. All the bits are cleared to 0 when reset.

Ref: PrimeCell® UART (PL011) - 3.3.7

UARTICR

The UARTICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

Ref: PrimeCell® UART (PL011) - 3.3.13

UARTFR

The UARTFR register is the flag register. After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1.

Ref: PrimeCell® UART (PL011) - 3.3.3

UARTDR

The UARTDR register is the data register.

Ref: PrimeCell® UART (PL011) - 3.3.1

UARTIMSC

The UARTIMSC register is the interrupt mask set/clear register. It is a read/write register.

Ref: PrimeCell® UART (PL011) - 3.3.10

UARTRIS

The UARTRIS register is the raw interrupt status register. It is a read-only register. On a read this register gives the current raw status value of the corresponding interrupt. A write has no effect.

Ref: PrimeCell® UART (PL011) - 3.3.11

UARTMIS

The UARTMIS register is the masked interrupt status register. It is a read-only register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect.

Ref: PrimeCell® UART (PL011) - 3.3.12

UARTICR

The UARTICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

Ref: PrimeCell® UART (PL011) - 3.3.13

ARM Interrupt Registers

The base address for the ARM interrupt register is 0x7E00B000. (Mapped to MMIO_BASE(0x3F000000) + 0xb000)

#define IRQ_BASE                (MMIO_BASE + 0xb000)
NameADDRESS
IRQ basic pendingIRQ_BASE + 0x200
IRQ pending 1IRQ_BASE + 0x204
IRQ pending 2IRQ_BASE + 0x208
FIQ controlIRQ_BASE + 0x20C
Enable IRQs 1IRQ_BASE + 0x210
Enable IRQs 2IRQ_BASE + 0x214
Enable Basic IRQsIRQ_BASE + 0x218
Disable IRQs 1IRQ_BASE + 0x21C
Disable IRQs 2IRQ_BASE + 0x220
Disable Basic IRQsIRQ_BASE + 0x224

ARM peripherals interrupts table
ARM peripherals interrupts table

Doc: https://cs140e.sergio.bz/docs/BCM2837-ARM-Peripherals.pdf

IRQ_BASIC_PENDING

The basic pending register shows which interrupt are pending.

Ref: BCM2837-ARM-Peripherals - p113

IRQ_ENABLE_2

Set to enable IRQ source 63:32

Ref: BCM2837-ARM-Peripherals - p117

Core Timer

#define CORE0_TIMER_IRQ_CTRL  ((unsigned int*)0x40000040)
#define CORE1_TIMER_IRQ_CTRL  ((unsigned int*)0x40000044)
#define CORE2_TIMER_IRQ_CTRL  ((unsigned int*)0x40000048)
#define CORE3_TIMER_IRQ_CTRL  ((unsigned int*)0x4000004C)

Ref: QA7_rev3.4 - 4.6

Local Timer

#define LOCAL_TIMER_CTRL      ((unsigned int*)0x40000034)
#define LOCAL_TIMER_IRQ_CLR   ((unsigned int*)0x40000038)

LOCAL_TIMER_CTRL

local timer control & status

Ref: QA7_rev3.4 - 4.11

LOCAL_TIMER_IRQ_CLR

The IRQ clear & reload register.

Ref: QA7_rev3.4 - 4.11

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